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1/11 L6388 may 2005 1 features high voltage rail up to 600 v dv/dt immunity 50 v/nsec in full temperature range driver current capability:400 ma source,650 ma sink switching times 70/40 nsec rise/fall with 1nf load 3.3v, 5v, 15v cmos/ttl inputs comparators with hysteresys and pull down internal bootstrap diode outputs in phase with inputs dead time and interlocking function 2 description the L6388 is an high-voltage device, manufac- tured with the bcd"off-line" technology. it has a driver structure that enables to drive inde- pendent referenced n channel power mos or ig- bt. the upper (floating) section is enabled to work with voltage rail up to 600v. the logic inputs are cmos/ttl compatible for ease of interfacing with controlling devices. high-voltage high and low side driver figure 2. block diagram logic uv detection level shifter bootstrap driver r s v cc lvg driver v cc 8 7 6 5 4 hin lin hvg driver hvg h.v. to load out lvg gnd vboot 3 2 1 cboot shoot through prevention uv detection r rev. 2 fi gure 1. p ac k age table 1. order codes part number package L6388 dip8 L6388d so8 L6388d013tr so8 in tape & reel so8 dip8
L6388 2/11 table 2. absolute maximum rating note: esd immunity for pins 6, 7 and 8 is guaranteed up to 900v (human body model) figure 3. pin connection (top view) table 3. pin description (*) the circuit guarantees 0.3v maximum on the pin (@ isink = 10ma). this allows to omit the "bleeder" resistor connected betwe en the gate and the source of the external mosfet normally used to hold the pin low. table 4. thermal data symbol parameter value unit v out output voltage -3 to v boot - 18 v v cc supply voltage - 0.3 to +18 v v boot floating supply voltage - 1 to 618 v v hvg high side gate output voltage - 1 to v boot v v lvg low side gate output voltage -0.3 to v cc +0.3 v v i logic input voltage -0.3 to v cc +0.3 v dv out /dt allowed output slew rate 50 v/ns p tot total power dissipation (t j = 85c) 750 mw t j junction temperature 150 c t stg storage temperature -50 to 150 c n. name type function 1 lin i low side driver logic input 2 hin i high side driver logic input 3 vcc i low voltage power supply 4 gnd ground 5 lvg (*) o low side driver output 6 out o high side driver floating reference 7 hvg (*) o high side driver output 8 vboot bootstrap supply voltage symbol parameter so8 minidip unit r th j-amb thermal resistance junction to ambient 150 100 c/w v cc hin lin gnd 1 3 2 4 lvg out hvg v boot 8 7 6 5 d97in517a
3/11 L6388 table 5. recommended operating conditions note 1: if the condition vboot - vout < 18v is guaranteed, vout can range from -3 to 580v (*): v bs = vboot - vout symbol pin parameter test condition min. typ. max. unit v out 6 output voltage note 1 580 v v bs (*) 8 floating supply voltage note 1 17 v f sw switching frequency hvg,lvg load cl = 1nf 400 khz v cc 3 supply voltage 17 v t j junction temperature -45 125 c table 6. electrical characteristics (v cc = 15v; t j = 25c) symbol pin parameter test condition min. typ. max. unit ac operation t on 1 vs 5 2 vs 7 high/low side driver turn-on propagation delay v out = 0v 225 300 ns t off high/low side driver turn-off propagation delay v out = 0v 160 220 ns t r 7,5 rise time c l = 1000pf 70 100 ns t f 7,5 fall time c l = 1000pf 40 80 ns dt 7,5 dead time 220 320 420 ns dc operation low supply voltage section v ccth1 3v cc uv turn on threshold 9.1 9.6 10.1 v v ccth2 v cc uv turn off threshold 7.9 8.3 8.8 v v cchys v cc uv hysteresis 0.9 v i qccu undervoltage quiescent supply current v cc 9v 250 330 a i qcc quiescent current v cc = 15v 350 450 a r dson bootstrap driver on resistance (**) v cc 125 ? bootstrapped supply voltage section v bsth1 8v bs uv turn on threshold 8.5 9.5 10.5 v v bsth2 v bs uv turn off threshold 7.2 8.2 9.2 v v bshys v bs uv hysteresis 0.9 v iq bs v bs quiescent current hvg on 250 a ilk high voltage leakage current v hvg = v out = v boot = 600v 10 a high/low side driver i so 5,7 source short circuit current v in = v ih (tp < 10 s) 300 400 ma i si sink short circuit current v in = v il (tp < 10 s) 500 650 ma
L6388 4/11 (**) rdson is tested in the following way: where i 1 is pin 8 current when v cboot = v cboot1 , i2 when v cboot = v cboot2 . figure 4. dead time waveforms definitions figure 5. propagation delay waveform definitions logic inputs v il 1, 2 low level logic input voltage 1.1 v v ih high level logic input voltage 1.8 v i ih high level logic input current v in = 15v 20 70 a i il low level logic input current v in = 0v -1 a table 6. electrical characteristics (continued) (v cc = 15v; t j = 25c) symbol pin parameter test condition min. typ. max. unit r dson v cc v cboot1 ? () v cc v cboot2 ? () ? i 1 v cc v ccboot1 , () i 2 ? v cc v ccboot2 , () -------------------------------------------------------------------------------------------------------------- = dt dt dt lin hin lvg hvg interlocking function 50% 50% 50% > dt 50% 50% 10% 90% ton toff > dt 10% 90% ton toff lin hin lvg hvg 50% 50% 50% 50% 50% > dt 50% 50% 50% 10% 90% ton toff > dt 10% 90% ton toff lin hin lvg hvg
5/11 L6388 3 input logic input logic is provided with an interlocking circuitry which avoids the two outputs (lvg, hvg) to be active at the same time when both the logic input pins (lin, hin) are at a high logic level. in addition, to prevent cross con- duction of the external mosfets, after each output is turned-off the other output cannot be turned-on before a certain amount of time (dt) (see figure 4). figure 6. typical rise and fall times vs. load capacitance figure 7. quiescent current vs. supply voltage for both high and low side buffers @25?c tamb 0 1 2 3 4 5 c (nf) 0 50 100 150 200 250 time (nsec) t r d99in1054 t f 0 246810121416v s (v) 10 10 2 10 3 10 4 iq ( a) d99in1055 3.1 bootstrap driver a bootstrap circuitry is needed to supply the high voltage section. this function is normally accomplished by a high voltage fast recovery diode (fig. 8a). in the L6388 a patented integrated structure replaces the external di- ode. it is realized by a high voltage dmos, driven synchronously with the low side driver (lvg), with in series a diode, as shown in fig. 8b an internal charge pump (fig. 8b) provides the dmos driving voltage . the diode connected in series to the dmos has been added to avoid undesirable turn on of it. 3.2 cboot selection and charging to choose the proper c boot value the external mos can be seen as an equivalent capacitor. this capacitor c ext is related to the mos total gate charge : the ratio between the capacitors c ext and c boot is proportional to the cyclical voltage loss . it has to be: cboot>>>cext e.g.: if q gate is 30nc and v gate is 10v, c ext is 3nf. with c boot = 100nf the drop would be 300mv. if hvg has to be supplied for a long time, the cboot selection has to take into account also the leakage losses. e.g.: hvg steady state consumption is lower than 200 a, so if hvg t on is 5ms, cboot has to supply 1 c to c ext . this charge on a 1 f capacitor means a voltage drop of 1v. the internal bootstrap driver gives great advantages: the external fast recovery diode can be avoided (it usually has great leakage current). this structure can work only if v out is close to gnd (or lower) and in the meanwhile the lvg is on. the charging time (t charge ) of the c boot is the time in which both conditions are fulfilled and it c ext q gate v gate --------------- =
L6388 6/11 has to be long enough to charge the capacitor. the bootstrap driver introduces a voltage drop due to th e dmos rdson (typical value: 125 ohm). at low fre- quency this drop can be neglected. anyway increasing the frequency it must be taken in to account. the following equation is useful to compute the drop on the bootstrap dmos: where q gate is the gate charge of the external power mos, r dson is the on resistance of the bootstrap dmos, and t charge is the charging time of the bootstrap capacitor. for example: using a power mos with a total gate charge of 30nc the drop on the bootstrap dmos is about 1v, if the t charge is 5 s. in fact: v drop has to be taken into account when the voltage drop on c boot is calculated: if this drop is too high, or the circuit topology doesn't allow a sufficient charging time, an external diode can be used. figure 8. bootstrap driver. v drop i ch e arg r dson v drop q gate t ch e arg ------------------- - r dson == v drop 30nc 5 s -------------- - 125 ? 0.8v ? = to load h.v. hvg a b lvg hvg lvg c boot to load h.v. c boot d boot v boot v s v s v out v boot v out
7/11 L6388 figure 9. v boot uv turn on threshold vs. temperature figure 10. v boot uv turn off threshold vs. temperature figure 11. v cc uv turn on threshold vs. temperature figure 12. v cc uv turn off threshold vs. temperature figure 13. output source current vs. temperature figure 14. output sink current vs. temperature -45 -25 0 25 50 75 100 125 5 6 7 8 9 10 11 12 13 v bsth1 (v) t j ( ?c ) t y p. @ vcc = 15v -45 -25 0 25 50 75 100 125 6 7 8 9 10 11 12 13 14 t y p. @ vcc = 15v v bsth2 (v) -45 -25 0 25 50 75 100 125 7 8 9 10 11 12 13 vccth1(v) t j ( ?c ) t y p. -45 -25 0 25 50 75 100 125 6 7 8 9 10 11 vccth2(v) t j ( ?c ) t y p. -45-250 255075100125 0 200 400 600 800 1000 current (ma) t j ( ?c ) t y p. @ vcc = 15v -45 -25 0 25 50 75 100 125 0 200 400 600 800 1000 current (ma) t j ( ?c ) t y p. @ vcc = 15v
L6388 8/11 figure 15. dip8 mechanical data & package dimensions outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a3.32 0.131 a1 0.51 0.020 b 1.15 1.65 0.045 0.065 b 0.356 0.55 0.014 0.022 b1 0.204 0.304 0.008 0.012 d 10.92 0.430 e 7.95 9.75 0.313 0.384 e2.54 0.100 e3 7.62 0.300 e4 7.62 0.300 f 6.6 0.260 i 5.08 0.200 l 3.18 3.81 0.125 0.150 z 1.52 0.060 dip-8
9/11 L6388 figure 16. so8 mechanical data & package dimensions outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 a2 1.10 1.65 0.043 0.065 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.007 0.010 d (1) 4.80 5.00 0.189 0.197 e 3.80 4.00 0.15 0.157 e 1.27 0.050 h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 l 0.40 1.27 0.016 0.050 k 0? (min.), 8? (max.) ddd 0.10 0.004 note: (1) dimensions d does not include mold flash, protru- sions or gate burrs. mold flash, potrusions or gate burrs shall not exceed 0.15mm (.006inch) in total (both side). so-8 0016023 c
L6388 10/11 table 7. revision history date revision description of changes january 2005 1 first issue may 2005 2 changed from preliminary data to final
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